The present invention relates to electronic and digital computer systems. More particularly, it relates to control elements within the CPU of such computer systems.
As has been noted in the above referenced co-pending application, Ser. No. 470,127 filed 2/28/83 of C. P. Ryan, et al, an aim of improved computer systems is the enhancement of the data throughput of the system. To this end, high speed cache memories have been provided which, in the interest of greater speed of operation, are operated on a store-into basis. That is, data which has been extracted from the main memory and manipulated or modified by the CPU is stored in the cache memory only; the modified data is ordinarily not returned to the main memory except under special circumstances. As also noted in the aforementioned co-pending application, and in co-pending application Ser. No. 511,616 filed 7/7/83 of T. Howell, et al, the computer system may include two or more CPUs operating with the one shared main memory. In such a system, the latest version of a data element may reside only in the cache memory of one of the CPUs. As noted in the aforementioned applications, means are provided for rendering direct access to the data in the cache associated with one CPU by demand from another CPU in the system.
Again, in the interest of enhancing the throughput of data in the computer system, the system is operated in accordance with a pipeline protocol. That is, a series of instructions are applied sequentially to the input of the system in successive cycle time slots of a computer without having to wait for the completion of the previous routine. Thus, with, for example, five time slots in the pipeline, there may be five different instructions simultaneously in successive stages of completion.
In the system set forth in the aforemention co-pending applications, whenever data is transferred into or out of the cache memory, a whole block of data is transmitted. In the exemplary embodiment, each block of data is comprised of eight words of data, while the CPU operates on as much as a double word or on as little as a single byte of an addressed word, the entire block of words including the addressed word is transferred for storage into the associated cache memory. Transfers of data from the CPU to the cache memory require considerably less time, usually, than the transfer of data from the main memory. This requires control of the data flow to assure that modified data is properly merged with the remainder of the block of data extracted from the main memory.